Display system with graphic fill-in

ABSTRACT

Television-type display system for displaying information in the form of bargraphs. Code words designating individual characters of bargraphs are read out of a random access memory and the characters are displayed at fixed normal locations on the display surface of the display device. Delay code words designating amounts of delay for fine positioning the top edges of the bars may be associated with the uppermost character of each bar. The system provides for filling in certain portions of the bars in the display of overlapping bargraphs to produce continuous, uniform bars.

United States Patent Gicca et al.

[ Dec. 11, 1973 DISPLAY SYSTEM WITH GRAPHIC FILL-IN 3,686,662 8/1972Blixt et al .1 340/324 AD 3,603,963 9/1971 Ward 340/324 A [75] lnvemms'a Bedford 3,678,498 7 1972 Nagamatsu et al. .1 178/30 C. Passavant, WestNewton; i a g Frammgham; Primary Examiner-Donald J. Yusko z ewtonAssistant Examiner-Marshall M. Curtis lg an a o Att0rneyNorman J.O'Malley et al. [73] Assignee: GTE Sylvania Incorporated,

Stamford, Conn. [57] ABSTRACT [22] Filed: .June 21, 1972 Television-typedisplay system for displaying information in the form of bargraphs. Codewords designating [21] Appl' 264969 individual characters of bargraphsare read out of a random access memory and the characters are dis- [52]US. Cl 340/324 AD, 178/30 played at fixed normal locations on thedisplay surface [51] Int. Cl. 006i 3/14 of the display device. Delaycode words designating [58] Field of Search 340/324 A, 324 AD; amountsof delay for fine positioning the top edges of 178/15, 30 the bars maybe associated with the uppermost character of each bar. The systemprovides for filling in [56] Ref r n es Cited certain portions of thebars in the display of overlap- UNITED STATES PATENTS ping bargraphs toproduce continuous, uniform bars.

3,678,497 7/1972 Watson et al. 340/324 AD 11 Claims, 12 Drawing FiguresDOT a/N DELAY CHARACTER MN OR DELAY ADDRESS CLOCK GENERA VIDEO AMPL(cgggMwoRo CHARACTER REFRESH MEMORY) DECODER CHARACTER DELAYl VIDEOBUFFER AMPL.

GRAPHIC CHARACTER 51 DATA AND HIGH TUDE Y 2 VIDEO BUFFER AMPI- AND VIDEOBUFFER 61 DELAY NEXT HORIZBiVERT SYNC FILL-IN VIDEO BUFFER GRAPHIC CLOCKFILL-IN D ETECTOR Y 2 CLOCK GEN.

DELAY MUX CONTROL 41 CLOCK DELAY 1 MUX DELAY 2 DELAY l MUX DELAY 2 DELAY1 COMPLETE DELAY 2 COMPLETE FAIENIEI] IIEE I I I975 SIIIIEI '1 [If 7503mm Eda oz o 0 0 X32 H 509mm time I QT P time IQ ml H Q JOWFZOQ x32 II I I I I I v QLHN PAIKNIEIJnu: n 1975 SHEET 5 CF 7 Fig.9.,

Fig. 8.

PAIENIEIIBEI: 1 1 I975 ROW Fig. 6A.

CODE FOR 6 DOTS DELAY CODE FOR

SOLID CHARACTER CODE FOR SOLID CHARACTER CODE FOR SOLID CHARACTER CODEFOR SOLID CHARACTER 37,1831 1 sum 80F 7 e DoTs DELAY Row FIRST CHARACTERSECOND' CHARACTER DISPLAY SYSTEM WITH GRAPHIC FILL-IN BACKGROUND OF THEINVENTION This invention relates to display systems. More particularly,it is concerned with apparatus for producing television-like displays ofinformation in graphical form.

Terminal display systems of the type for displaying business data from acomputer on television monitors are well-known. These systems aregenerally similar. A controller is employed to communicate message toand from a host computer in which data processing tasks are performed.Information to be displayed is transmitted from the controller torefresh memories which store the information being displayed in binarycode format. The display stations each employ a standard closedcircuittelevision monitor and keyboard which permits the operator tocommunicate with the host computer.

Typically display systems of this general type display information inalphanumeric form. Alphanumeric codes representing the characters to bedisplayed are loaded from the host computer through the controller andinto a refresh memory associated with a display device at the displaystation. The alphanumeric code words are placed in particular storagepositions in the refresh memory. Each storage position designates aspecific row and column character location on the face of the displaydevice. Each display station includes a video generator which receivesthe code words as they are repeatedly read out of the associated refreshmemory in timed relationship with the sweeping of the raster scanlinepattern. The code words read out for each scanline are converted into aseries of data bits. These bits are gated into the video stream to thedisplay device to cause the image of each character to be constructed ofseveral series of dots written during several scanlines. The characterrepresented by a code word is displayed on the face of the displayeddevice in the normal location designated by its storage position in therefresh memory.

Although display terminals of this type are satisfactory for displayingalphanumeric characters in a regular row and column array of text, theydo not permit the display of true curves, histograms, or bargraphs.Since characters may be positioned only in normal locations, graphicaldisplays of information are relatively crude. High quality graphicpresentations may be obtained by the use of random access displaydevices of the type in which deflection amplifiers guide the beam of acathode ray tube through a pattern of movement permitting characters tobe displayed at almost any position on the display surface. However,high-speed, high-quality random access display terminals of this typewhich permit complete freedom of beam movement and character locationare considered inordinately expensive for use in routine businessapplications.

An improved display system which provides high quality displays ofgraphical information on standard television displays is described andclaimed in application Ser. No. 264,970 filed concurrently herewith andentitled Television Type Display System for Displaying Information inthe Form of Curves or Graphs. Systems in accordance with this inventionmay be employed to display the information in the form of bargraphs andcurves which are esthetically pleasing and exhibit a high degree ofaccuracy. The system also permits the display of sets of curves whichmaintain their continuity and smoothness throughout, including atcrossover points. In addition, the system is capable of producingbargraphs of uniform appearance and with their upper edges accuratelypositioned.

However, itis sometimes desirable in displaying graphical information inbargraph form to utilize composite or overlapping bargraphs of differentdensity. The system as described in the aforementioned application whileproviding for the display of information in bargraph form is limited inits capability of producing overlapping bargraphs. Since portions of therefresh memory which usually designate specific row and col- I umndisplay locations on the display device are also needed to containinformation for accurate positioning of the upper edge of each bargraph,the refresh memory lacks sufficient storage positions to contain datafor all the required characters and also all the necessary positioninginformation.

SUMMARY OF THE INVENTION Display systems in accordance with the presentinvention permit the high quality display of overlapping or compositebargraphs. A system displays characters so as to produce overlappingbargraphs on a video display means of the type producing images on adisplay surface by selectively writing on the display surface whilerepeatedly sweeping a raster scanline pattern over the display surface.The system includes character data memory means for storing characterdata in a plurality of storage positions. An addressing means causescharacter data to be read out of the character data memory meansbyaddressing the storage positions in a predetermined sequence.

A video signal generating means is coupled to the character data memorymeans and in response to character data being read out of the characterdata memory means generates video signals for producing images relatedto the character data on the display surface so that images related tothe character data are produced in a predetermined location on thedisplay surface. The system also includes a fill-in means which iscoupled to the video signal generating means. The fill-in means causesthe video signal generating means to repeat generating the video signalsfor producing images related to the character data so that imagesrelating to the character data are also produced in one or more otherlocations on the display surface.

The system thus provides the capability for repeating the display ofimages related to the character data in more than one location on thedisplay surface even though only a single storage position is used tostore the character data. Storage capability is thus made available forcontaining necessary information to permit accurate positioning ofcertain of the character images as required in the construction of highquality overlapping or composite bargraphs.

BRIEF DESCRIPTION OF THE DRAWINGS Additional objects, features, andadvantages of display systems in accordance with the present inventionwill be apparent from the following detailed discussion together withthe accompanying drawings wherein:

FIG. 1 is a block diagram of a display system employed in the presentinvention;

FIG. 2 is a block diagram of a video generator in accordance with thepresent invention for use in the system illustrated in FIG. 1;

FIG. 3 is a detailed block diagram of a graphic fill-in control sectionof the apparatus;

FIG. 4 is a detailed block diagram of a multiplexer and shift registersection of the apparatus;

FIG. 5 illustrates several graphic characters which may be employed inthe display systems of FIG. 1 in the construction of bargraphs;

FIG. 6A is a chart or map of a portion of a random access digitalstorage type refresh memory employed in the system of FIG. 1;

FIG. 6B is a representation of a portion of the display surface of adisplay device illustrating the resulting display produced from the dataencoded in the refresh memory of FIG. 6A;

FIG. 7A is also a map of a portion of a refresh memory;

FIG. 7B is a representation of a portion of the display surfaceillustrating the resulting display produced from the data encoded in therefresh memory of FIG. 7A in the absence of the fill-in capability inaccordance with the present invention;

FIG. 7C is a representation of a portion of the display surfaceillustrating the resulting display produced from the data encoded in therefresh memory of FIG. 7A employing apparatus in accordance with thepresent invention;

FIG. 8 is a representation of a portion of a display surfaceillustrating the display of several overlapping bargraphs constructed byapparatus in accordance with the present invention; and

FIG. 9 is another representation of a portion of a display surfaceillustrating the display of a different form of overlapping bargraphs.

DETAILED DESCRIPTION OF THE INVENTION General FIG. 1 is a block diagramof an entire display system which at the level of detail shown resemblesmany known systems as well as systems in accordance with the presentinvention. FIG. 2 is a detailed block diagram of a video generator inaccordance with the present invention which is employed in the system ofFIG. 1. The system includes a host computer 10 together with associatedperipheral equipment and software and a controller 12 which communicateswith the computer through a suitable interface arrangement 11. Thesystem may contain several display stations each including a refreshmemory 16, a video generator 17, a video display device 18, and akeyboard 19. Data is transferred to th refresh memories 16 through aninput/output buffer 15. The refresh memories 16 and video generators 17are controlled by a display controller 14 which is also connected to theinput/output buffer 15. The keyboards 19 of the individual displaystations are connected to the computer 10 through a keyboard interface13 and the controller 12.

Apparatus of the type shown generally in FIG. 1 typically is employed todisplay alphanumeric characters in text row-column locations, or normallocations, on the face of the television display device 18 at a displaystation. More specifically, the refresh memory 16 is divided into anarray of storage positions each corresponding to a normal locationwithin a row and column arrangement on the display surface. Each storageposition stores a single code word representing an alphanumericcharacter and each location provides space for displaying a singlecharacter. For example, the storage positions in the memory and thecharacter locations on the display surface may be arranged in verticalcolumns and 40 horizontal rows to provide for displaying up to 4,000characters of text on the surface of the display device.

Heretofore, when systems of this general type have been employed todisplay graphical information, the limitation of positioning charactersonly in normal locations severely limited the accuracy and the estheticsof the resulting display. Each character was limited to being displayedin its appropriate normal location by row and column. In contrast,systems in accordance with the aforementioned application being filedconcurrently herewith permit shifting of individual characters fromtheir normal locations, thus providing a display of graphicalinformation which more clearly represents a curve. This system alsopermits shifting the location of a character to permit the constructionof bargraphs in which the top edges are precisely located to within afraction of the dimension of a character location, as illustrated inFIG. 63. Because of limitations in the memory and the manner in which itis addressed, as will be explained in detail hereinbelow, this systemdoes not permit the construction of overlapping or composite bargraphswith precisely positioned upper edges. Systems in accordance with thepresent invention do permit the display of overlapping bargraphs withthe uppr edges of each portion accurately located to provide displays asillustrated by FIGS. 8 and 9.

As an example of a specific embodiment for purposes of discussionherein, each of the 4,000 normal locations on the surface of the displaydevice occupies a 6X10 dot matrix, 6 dots horizontally and 10 dotsvertically. The image of a character is constructed by selectivelywriting dots in th vertical dot columns of 10 dot positions each duringtracing of 6 vertical scanlines. In the specific embodiment underdiscussion, the scanlines are traced vertically downward and odd andeven scanlines are interlaced during sweeping of alternating fields.Thus, 6 vertical scanlines, 3 in each field, are required to constructthe image of a character in a 6X10 dot matrix location. In order toprovide separation between alphanumeric characters in adjacentlocations, each alphanumeric character is confined to a 5X7 dotconfiguration. However, the present invention is concerned not withalphanumeric characters but with special graphic characters which aredisplayed so as to utilize up to the full 6X10 dot matrix as will beexplained hereinbelow. As will be made apparent in further discussion ofthe system in accordance with the present invention, the characters maybe shifted vertically from their normal locations and positioned in oneof 400 possible locations for each vertical column, or 40,000 possiblelocations on the face of the display. The characters are shifted inincremental divisions of l dot, or 1/10 of a character location in thevertical dimension.

Codes designating the characters to be displayed are transferred fromthe computer 10 to appropriate storage positions in the refresh memory16. If a character is to be positioned on the display in a locationshifted from a normal location, a delay code is stored in the storageposition designating the previous row of the same column. The delay codedesignates the amount the associated character is to be delayed orshifted vertically downward from what would be its normal location. Thestorage positions in the memory are read out vertically from top tobottom within a single column in timed relationship with the tracing ofeach scanline by the display controller 14. Thus, during each field,each column of storage positions is addressed in sequence for threesuccessive scanlines. The total number of active scanlines for acomplete frame of two fields is 600.

In the specific embodiment as illustrated, three different types of codewords may be entered in the refresh memory 16 from the computer 10. Thecode words, which contain eight binary bits, designate either analphanumeric character, a special graphic character, or an amount ofdelay. The following table explains the nature of the three types ofcode words.

Bit No. 8 7 6 5 4 3 2 1 OAxxxxxx Oforeighthbit indicates code foralphanumeric character. Seventh bit (A) is 0 for low amplitude or 1 forhigh amplitude. xxxxxxisbinary number designating one of 64 possiblealphanumeric characters. 1 for eighth bit and 1 for sixth bit indicatescode for graphic character. Seventh bit (A) is 0 for low amplitude or 1for high amplitude. y y y y y is binary number designating one of 32possible graphic characters. l for eighth bit and 0 for sixth bitindicates code for delay. 2 z z z z is binary number designating anamount of delay in number of vertical dots.

Alphanumeric Character Code Word Graphic Character Code Word yyyyy DelayCode Word In the system under discussion, the display device 18 mayinclude the capability of displaying a character with relatively high orrelatively low brightness levels. The seventh bit for the character codeword is either a l or a 0 to designate the brightness amplitude.

The various code words are loaded into the storage positions of therefresh memories 16 from the computer through the input/output bufferduring appropriate times in the operating cycles of the apparatus undercontrol of the controller 12 and display controller 14. The code wordsare read out of the refresh memory 16 to the video generator 17 underthe control of the display controller 14 in proper timed relationshipwith the sweeping of the raster scan line pattern of the display device18. The display controller 14 supplies the timing and control signals tothe refresh memory 16 and to the video generator 17. These signalsinclude the horizontal and vertical synchronizing signals for thedisplay device as well as various coordinated clock pulse signalsoccuring at the scanline rate, the character location rate, and theindividual character bit or dot position rate. These signals arerepetitive over each operating cycle of the apparatus during thesweeping of a complete raster scanline frame over the face of thedisplay device 18. The display controller 14 is, therefore, an elementof straightforward design for providing a multitude of synchronizedpulses at different frequencies which are appropriately gated to therefresh memory 16 and video generator 17 so as to properly coordinateoperations throughout the system.

As a code word is read out of its storage position in the refresh memory16 by the display controller 14, the

code bits designating the character or the amount of delay are loadedinto the character or delay code register 27 of the video generator 17as shown in FIG. 2. At the same time, the portion of the code worddesignating whether the code is for a delay, an alphanumeric character,or a graphic character, as well as the bit indicating the amplitude, isdecoded by a decoder 25 and loaded in the delay, alphanumeric orgraphic, and amplitude indication register 28. Also while the code wordis being read out of the storage position in the memory, the decoder 25produces a delay next"-signal to a graphic fill-in control 60 if thedecoder detects that the code word is for a delay. The information onthe particular dot column or scanline is received from the displaycontroller 14 and loaded into the dot column address register 26.

The code in the character or delay code register 27 is then applied tothe alphanumeric character generator 29, the graphic character generator30, or the delay register 31 as determined by the appropriatealphanumeric, graphic, or delay signal from the delay, alphanumeric orgraphic, and amplitude indication register 28. The character generators29 and 30 are read-only memories of the well-known type which are widelyemployed to convert digital code designations to the appropriate signalsfor producing the dot images for the particular scanline of thecharacter. The particular scanline is identified by the data from thedot column address register 26. If the code from the character or delaycode register 27 is a delay code which is transferred to the delayregister 31, the delay arrangement 40 operates to control handling ofthe associated character code which is read out from the next storageposition to be addressed in the refresh memory.

The graphic fill-in control 60 responds to a graphic signal from thedelay, alphanumeric or graphic, and amplitude indication register 28indicating that the code in the character or delay code register 27 is agraphic character in combination with a delay next signal from thedecoder 25 indicating that the next storage position in sequence isbeing read out and contains a delay code. If this set of conditionsoccurs, such information remains in the graphic fill-in control 60 to beemployed at a later step in the processing of the graphic characterdata, as will be explained hereinbelow.

The video buffer control 48 causes the character data from eithercharacter generator 29 or 30 to be entered in the no delay video buffer45 if there was no previous delay code for it to be associated with. Ifthe character data is associated with a delay, it is loaded into thedelay 1 video buffer 46 or the delay 2 video buffer 47. The systemutilizes the delay 1 video buffer 46 and the delay 2 video buffer 47 inalternation.

Character data is read out of the video buffers 45, 46, and 47 by themultiplexers 50 and 51 together or by multiplexer 51 alone under controlof the respective multiplexer controls 41, 42, and 43. The appropriatemultiplexers 50 and 51 or 51 are selected by the multiplexer controlsdepending on the amplitude signal. The appropriate multiplexer controls41, 42, and 43 operate at the proper time with respect to the scanlinebeing traced to cause data to be transferred from the video buffers 45,46, and 47 to the appropriate shift registers 52 and 53 or 53 and fromthere to a summing network 54 where it is combined with thesynchronizing signals to produce the composite video signal. Amplitudeinformation is available by virtue of there being an output either fromboth of the shift registers 52 and 53 or from only the shift register53, and this information may be utilized by employing any of varioustechniques to pro duce displays of two different intensities.

The no delay multiplexer control 41 enables the proper multiplexers 50and 51 or 51 to read out the no delay video buffer 45 at the proper timeto cause the resulting image of the data to appear in the normallocation on the surface of the display device. The delay arrangement 40processes the delay information in the delay register 31 so as to causethe delay 1 multiplexer control 42 or the delay 2 multiplexer control 43to read out the associated character data in the delay 1 video buffer 46or the delay 2 video buffer 47 at the proper time to cause the resultingimage of the data to appear in a location on the display surface shiftedvertically downward by an amount determined by the delay code.

If the graphic fill-in control 60 has stored therein informationindicating a fill-in situation as applied to the graphic character datastored in the video buffer 45, 46, or 47, then upon read out of thegraphic character data from the buffer the graphic fill-in control 60produces an enabling signal. This signal activates the fill-in videobuffer 61 and the character data being supplied by the buffer 45, 46, or47 to the shift register 53 through the low and high amplitudemultiplexer 51 is caused to be loaded in the fill-in video buffer 61. Anamplitude detector 62 which is connected to the two shift registers 52and 53 detects the amplitude signal and this data is also loaded intothe fill-in video buffer 61.

A fill-in multiplexer control 63 enables the proper multiplexers 50 and51 or 51 to read out the fill-in video buffer 61 repeatedly at theproper times to cause the resulting images of the data to appear innormal locations on the surface of the display device. Operation of thefill-in multiplexer control 63 is terminated by a signal from thegraphic fillin control 60 indicating that the delay arrangement 40 hascompleted measuring the delay which generated the delay next signal toactivate the graphic fill-in control 60 and the character associatedwith that delay is now to be read out of either the delay 1 video buffer46 or the delay 2 video buffer 47 and applied to the appropriate shiftregisters 52 and 53 or 53.

Detailed Operation No FillIn A detailed explanation of the manner inwhich the apparatus of the invention operates to produce displays oftext in which the characters appear in their normal locations by rowsand columns is included in the aforementioned application filedconcurrently herewith. The aforementioned application also explains thedetails of operation of the system in order to cause a char acter to bedisplaced vertically downward a precise distance from its normallocation by a delay arrangement which is the same as that describedherein. Systems in accordance with the present invention may also beemployed to display alphanumeric text and curves, but the discussionherein will be limited to its use in producing vertical bargraphs.

FIG. illustrates examples of graphic characters which may be employed toconstruct bargraphs on the surface of a display device in accordancewith the present invention. Specific characters are designated in the8-bit code for graphic characters as explained hereinabove. Each graphiccharacter in FIG. 5 is positioned in the 6X10 dot matrix of a characterlocation. Graphic characters (a), (b), (c), and (j) are solid characters(every dot). Graphic characters ((1), (e), and (f) are half-tonecharacters (every other dot), and characters (g), (h), and (i) arequarter-tone characters (every fourth dot).

These characters may be employed to produce bargraph displays of varioustypes, such as illustrated in FIGv 68. By employing the apparatus in themanner described in the aforementioned application, the height of eachbar can be positioned within an accuracy of one dot 1/10 of the verticalheight of a character location), thus permitting precise positioning ofthe upper edge of the bar. Operation of the apparatus of FIGS. 1 and 2to produce such a display may be understood by reference to the map ofaportion of the memory as shown in FIG. 6A. The resulting portion of thedisplay is illustrated in FIG. 68. For purposes of illustration, thesolid graphic character (a) of FIG. 5 is employed in this example.

The following is a description of the manner in which the apparatusoperates in accordance with the explanation in the aforementionedapplication in order to produce a single bargraph as illustrated in FIG.68 without the need for the fill-in sections of the apparatus. As thestorage positions in the memory for the column as ar ranged in FIG. 6Aare addressed in timed relationship with an appropriate scanline, thedelay code word for 6 dots delay is read out first and applied to thevideo generator 17. The first five bits which designate the amount ofdelay are loaded in the character or delay code register 27. The decoder25 decodes the eighth and sixth bits as indicating a delay and entersthis information in the delay, alphanumeric and amplitude indicationregister 28.

When the data is read out of the input registers 26, 27, and 28, thepresence of a delay signal from the register 28 activates a delaycontrol 32. The delay control 32 enables the delay register 31 on asubsequent clock pulse so that the delay code from the character ordelay code register 27 is placed in the delay register 31. The delaycontrol 32 holds the delay code in the delay register 31 for a period oftime equivalent to the tracing of the scanline through 10 dots, thevertical dimension of a character location. This period of time isdetermined by the period of the clock pulses applied to the delaycontrol 32. On the clock pulse upon termination of this period (when thedata for the solid character read out from the third row of the columnis being loaded into the delay 1 video buffer 46 or the delay 2 videobuffer 47 as will be explained), the delay control 32 produces a delay 1or delay 2 signal. The delay control 32 includes a flip-flop arrangementwhich is caused to be triggered by each delay signal and in effectdivides by two so that every other delay code is processed as a delay 1and intervening delay codes are processed as a delay 2. Assuming a delay1 signal is produced by the delay control 32, the delay 1 signalactivates a delay 1 counter 34 causing a count represented by the delaycode in the delay register 31 to be loaded into the delay 1 counter 34.At the same time a delay 1 clock generator 33 is also activated. Thedelay I clock generator 33 produces periodic clock pulses at the dotposition rate. When the delay 1 clock generator 33 has provided theproper number of clock pulses (six in this example) to the delay 1counter 34 causing the delay 1 counter to count down from the delay ofsix received from the delay register 31 to a count of zero, a delay 1complete" signal is produced by the delay 1 counter. This signaldeactivates the delay 1 clock generator 33 and is also applied to thedelay 1 multiplexer control 42.

When the delay code from the character or delay code register 27 isapplied to the delay register 31, the next storage position in therefresh memory 16 is read out. Thus, the code word for the solidcharacter is read out of the third row and placed in the character ordelay code register 27, and the indication that it is a graphiccharacter as determined by the decoder 25 and the amplitude informationis stored in the delay, alphanumeric or graphic, and amplitudeindication register 28. The graphic signal, character code, and dotcolumn information are applied to the graphic character generator 30from the input registers 28, 27, and 26, respectively. The graphiccharacter generator 30 thus produces the appropriate data bits forwriting the image of the character in the appropriate dot column of thecharacter location.

The data bits pertinent to the solid character are applied to the videobuffers 45, 46, and 47 by the graphic character generator 30. The videobuffer control 48 receives the delay 1 signal from the delay control 32.in response to the delay 1 signal the video buffer control 48 inhibitsthe enabling signal to the no delay video buffer 45 on the next clockpulse, and instead produces an enabling signal to the delay 1 videobuffer 46 on the clock pulse. Thus the data bits pertinent to the solidcharacter from the graphic character generator 30 and the amplitudeinformation from the delay, alphanumeric or graphic, and amplitudeindication register 28 are loaded into the delay 1 video buffer 46.

The character data information remains stored in the delay 1 videobuffer 46 until the delay 1 counter 34 completes its countdown asexplained and the delay 1 complete signal is transmitted to the delay 1multiplexer control 42. In response to the delay 1 complete signal, thedelay 1 multiplexer control 42 produces an enabling signal to theappropriate gates of either both the low amplitude multiplexer 50 andthe low and high amplitude multiplexer 51 or only to the low and highamplitude multiplexer 51 depending upon the amplitude information fromthe delay 1 video buffer 46. In the present example, the enabling signaloccurs six dot positions of movement of the scanline later than if therewere no delay and the data were being transferred from the no delayvideo buffer 45. The data bits pertinent to the character are thustransferred through the appropriate multiplexers 50 and 51 or 51 to theassociated parallel-to-serial shift registers 52 and 53 or 53. The bitsare clocked out of the shift registers at the rate of one bit for thetracing of a scanline through one dot position, and pass through thesummation network 54 to become part of the composite video signal to thedisplay device. As illustrated. by the solid character labeled firstcharacter in FIG. 6B, by delaying the data bits for each scanline by sixdot positions, the image is constructed in a location which is 6 dotslower in the display than its normal location.

The storage position for the fourth row of the column is read out of thememory in proper timed relationship with the tracing of each scanline.The code bits designating the solid character are loaded into thecharacter or delay code register 27. The decoder 25 decodes theinformation in the eighth, seventh, and sixth bits and loads informationidentifying the code as designating a graphic character and also thedata on the amplitude in the delay, alphanumeric or graphic, andamplitude indication register 28.

The data in the input registers 26, 27, and 28 is applied to thecharacter generators 29 and 30. Since the delay, alphanumeric orgraphic, and amplitude indication register 28 produces a graphic signal,only the graphic character generator 30 is enabled.

The video buffer control 48 receives clock pulses at the characterlocation scanning rate. In response to each clock pulse, the videobuffer control 48 enables the no delay video buffer 45 unless a delay 1or delay 2 signal is present as explained previously. Since there is nodelay 1 or delay 2 signal present, the no delay video buffer 45 isenabled and the character data from the graphic generator 30 togetherwith the amplitude indication from the delay, alphanumeric or graphic,and amplitude indication register 28 are loaded into the no delay videobuffer 45.

The character data stored in the no delay video buffer 45 is read outunder control of the no delay multiplexer control 41. The no delaymultiplexer control 41 operates on periodic clock pulses which occur atthe character location scanning rate. Since there is no delayinformation being applied to the no delay multiplexer control 41 toindicate that the no delay video buffer 45 contains anything exceptcharacter data which is not to be delayed, the no delay multiplexercontrol 41 is not inhibited. A clock pulse causes the no delaymultiplexer control 41 to operate in timed relationship to the tracingof the scanline to enable either both the low amplitude multiplexer 50and the low and high amplitude multiplexer 51 or only the low and highamplitude multiplexer 51 depending upon the amplitude signal from the nodelay video buffer 45. The data bits relating to the character aretransferred in parallel from the no delay video buffer 45 to theappropriate parallel-to-serial shift registers 52 and 53 or 53.

Ten bits of character data are entered into the shift registers 52 and53 or 53 and are clocked out in series at the dot position rate to enterthe video stream by way of the summing network 54. Each bit enters thevideo stream in timed coordination with the tracing of the scanlinethrough the corresponding dot column position at the normal location onthe display surface. The series of data bits from the shift registers 52and 53 or 53 are combined with the horizontal and vertical synchronizingsignals from the display controller 14 to produce the composite videosignal which is transmitted to the display device 18 to construct theimage of the appropriate dot column of the character in its normallocation. Upon completion of sweeping through a complete frame of theraster scanline pattern, the image of the character is completelyconstructed in dot matrix form in its normal location as illustrated inthe fourth row in FIG. 6B and labeled second character. As shown in FIG.6B, portions of the two characters overlap, but the images of thecharacters are such that the entire bar is uniform in appearance.

The code words for the solid graphic character from the fifth and sixthrows are read out and processed with no delay as explained previously toproduce a continuous bar extending to the desired baseline of the graph.

Similarly, code words for the graphic characters (b) through (j) of FIG.5 may be utilized to produce various graphical displays. Each bar may beseveral character columns wide. For the graphic characters (a), (b), and(c) the upper levels may be positioned within one dot. In order for thebars produced with the characters (e) through (i) to appear uniform, thedelay must be in even numbers of dots. Detailed Operation Fill-In Thedisplay system in accordance with the present invention may also beemployed to display information in overlapping bargraph form asillustrated in FIGS. 8 and 9. In each group of bars illustrated, theupper bar is constructed of quarter-tone characters, the intermediatebar is constructed of half-tone characters, and the lower bar isconstructed of solid characters. The upper edge of each bar ispositioned precisely by delaying the first character of that type forthe desired number of dots.

However, since the delay information required to properly position thefirst character of each type with respect to its normal locationrequires a storage position in the memory, that storage position cannotbe used to contain a graphic character code word for the precedingcharacter. The problem caused by this situation is illustrated by thememory map of FIG. 7A and the resulting display shown in FIG. 7B. Asillustrated in FIG. 7B, the upper edge of the solid character stored inthe third row of the memory is shifted six dots downward from the normallocation for the third row. Since the last previous half-tone characteroccupies the normal location for the first row, there is a gap in thenormal location for the second row and the first six dot positions ofthe third row. The system of the present invention provides for fillingin this gap by repeating the half-tone character of the first row in thesecond and third rows to produce the resulting display as illustrated inFIG. 7C.

The system operates to read out the code word for the half-tonecharacter from the storage position for the first row of the memory andprocess the code word in the manner explained previously to cause thehalftone character to be displayed as shown in the normal location forthe first row of FIG. 7C. In addition, when the code for the half-tonecharacter is being applied to the graphic character generator 30 fromthe character or delay code register 27 and a graphic signal is beingproduced by the delay, alphanumeric or graphic, and amplitude indicationregister 28, the code word for six dots delay in the second column isbeing read out of the storage position for the second column causing thedecoder 25 to produce a delay next signal to the graphic fill-in control60.

The graphic fill-in control 60 is illustrated in greater detail in FIG.3. The portion of the control for processing data in the presentsituation includes an AND gate 71 to which is applied the graphic anddelay next signals. The output of the AND gate 71 is applied to a gate75. The gate 75 has an inhibiting input which is the output of an ORgate 74 having input connections from the delay control 32. Theseconnections cause the gate 75 to be inhibited if there is a previousdelay situation as will be explained later in this application. Theoutput of the gate 75 is applied to the D input of a D-type flipflop 78which is clocked at a rate equal to the character location scanningrate.

The output of the D-type flip-flop 78 is applied to an AND gate 81having another input from the no delay multiplexer control 41. Theoutput of the AND gate 81 causes the flip-flop 78 to be cleared and isapplied through an OR gate 82 directly to the fill-in video buffer 61 asa loading or enabling signal and to the .I

input of a J-K flip-flop 85. The .I-K flip-flop 85 is clocked at a rateequal to the dot position scanning rate. The output of the J-K flip-flop85 is applied to an AND gate 86. Periodic clock pulses at the characterlocation scanning rate are applied at the second input of the AND gate86. The output of the AND gate 86 is applied to the fill-in multiplexercontrol 63.

Delay 1 complete and delay 2 complete signals from the respective delay1 and delay 2 counters 34 and 36 are applied through an OR gate 83 to agate 84. An inhibiting input to the gate 84 is provided from the outputof the OR gate 82, the loading signal to the fill-in buffer 61. Theoutput of the gate 84 is applied to the K input of the .l-K flip-flop85.

In the example under discussion, as illustrated by FIGS. 7A and 7C,while the half-tone character code for the first row is being applied tothe graphic character generator 30, the graphic signal from the delay,alphanumeric or graphic, and amplitude indication register 28 and thedelay next signal from the decoder 25 are applied to the AND gate 71. Anoutput signal from the AND gate 71 passes through the gate 75 since, inthe present example, it is not inhibited by a delay in process in thedelay register. The signal is applied to the D input of the D-typeflip-flop 78.

When the code for the half-tone character of the first row is loadedinto the no delay video buffer 45, the clock pulse to the flip-flop 78sets the flip-flop since there is a signal at its D input. On the nextclock pulse at the no delay multiplexer control 41, which occurs acharacter location time later, the half-tone character data is read outfrom the no delay video buffer 45 and the AND gate 81 passes the sameclock pulse. This pulse passes through the OR gate 82 and is applied tothe fill-in video buffer 61 as a loading signal. It also causes theD-type flip-flop 78 to be cleared to its reset condition. Thus, the databits being read out of the no delay video buffer 45 through either thelow and high amplitude multiplexer 51 and the low amplitude multiplexer50 to the appropriate shift registers 52 and 53 or 53 are also appliedto the fill-in video buffer 61 to be stored therein. At the same timethe amplitude detector 62 by virtue of its being connected to both themultiplexers 50 and 51 detects the associated amplitude signal to bestored in the fill-in video buffer 61. Thus, while the code for thehalf-tone character for the first row is read out and the image for thecharacter is caused to be displayed in its normal location, labelednormal character in the first row of FIG. 7C,in addition the data bitsrelating to the character are placed in the fill-in video buffer 61.

The code word for six dots delay in the second row of the memory and thecode word for the associated solid character in the third row areprocessed as explained previously. While this information is beingprocessed, the periodic clock pulses at the character location rateapplied to the AND gate 86 of the graphic fillin multiplexer control 63.The pulses occur in proper timed relationship with the tracing of thescanline so as to cause the fill-in multiplexer control 63 to read outthe character data from the fill-in video buffer 61 through theappropriate multiplexers 50 and 51 or 51 to produce images in succeedingnormal locations. The first occurrence of reading out the fill-in videobuffer 61 causes the character image for the scanline to be written inthe second row as illustrated in FIG. 7C. A character location timelater, the next pulse from the fill-in multiplexer control 63 causes thecharacter image to be repeated in the third row as illustrated in FIG.7C. These two character images are labeled fill-in characters in FIG.7C.

During the first six bits of tracing a scanline for the third rowlocation, the half-tone character image is produced. Since the six dotdelay countdown is now complete, a delay 1 complete or delay 2 completesignal from the appropriate delay counter 34 or 36 causes theappropriate multiplexer control 42 or 43 to read out the solid characterdata from the appropriate video buffer 46 or 47. The solid character isthus produced six dots delayed from its normal location as shown in FIG.7C and labeled delayed character.

The delay complete signal is also applied to the OR gate 83 of thegraphic fill-in control 60. This pulse is passed by the OR gate 83 andthe AND gate 84 since there is no inhibiting signal from the OR gate 82.This signal is applied to the K input of the J-K flip-flop 85 so thatthe clock pulse to the flip-flop resets the flipflop. Thus, the graphicfill-in control 60 is returned to its quiescent state with the AND gate86 inactive so that subsequent clock pulses thereto will not cause thefill-in multiplexer control 63 to be activated. Thus, the fill-in videobuffer 61 is not read out subsequent to the writing of images in thenormal location for the third row as illustrated in FIG. 7C. I

The delayed solid character from the third row of the memory isdisplayed as illustrated and labeled delayed character in FIG. 7Coverlapping the last four dot positions of the half-tone character inthe normal loation location the third row. The code words in the fourth,fifth, and sixth rows are read out and the images pro duced in thefourth, fifth, and sixth rows of the display as illustrated in FIG. 7Cin the usual manner as explained previously when there is no delaysituation.

Thus, the system in accordance with the invention as described detectsthe need for a fill-in when writing graphic characters for constructingbargraphs and fills in the gap which would otherwise exist as in thesecond and third row locations as shown in FIGS. 7B and 7C. Thus, thesystem may be employed to display overlapping and composite bargraphs ofthe type illustrated in FIGS. 8 and 9.

A detailed block diagram of a multiplexer and its associated shiftregister which operate to permit the superimposing of characters as inthe third and fourth rows of the display of FIG. 7C is shown in FIG. 4.The low and high amplitude multiplexer 51 and its associated shiftregister 53 are illustrated. The other multiplexer 50 and shift register52 are similar. The shift register 53 includes flip-flop stagesFFl-FF10, one for each data bit in a character dot column. Theoccurrence of a clock pulse at the C input sets each flip-flop toproduce an output signal at its output if there is a signal present atits D input. If no signal is present at the D input, a clock pulseresets the flip-flop and no output signal is produced.

The multiplexer 51 includes 10 groups of four AND gates 91-100, a groupassociated with each flip-flop. Each AND gate has two inputs. A firstinput of one AND gate of one group 91 is connected to the no delay videobuffer 45 to receive the first character data bit therefrom and thesecond input is connected to the no delay multiplexer control 41 toreceive a no delay readout pulse therefrom. A second AND gate of thegroup 91 is connected to the delay 1 video buffer 46 to receive thefirst character data bit therefrom, and to the delay 1 multiplexercontrol 42 to receive a delay I readout pulse therefrom. The third gateof the group 91 is connected in similar fashion to receive the firstcharacter data bit from the delay 2 video buffer 47 and a delay 2readout pulse from the delay 2 multiplexer control 43. In the samemanner, the fourth gate of the group 91 is connected to receive thefirst character data bit from the fill-in video buffer 61 and a fill-inreadout pulse from the fill-in multiplexer control 63.

The AND gates 92 of the second group are appropriately connected toreceive the second character data bits from the video buffers 45, 46,47, and 61 and the readout pulses from the multiplexer controls 41, 42,43, and 63. The other groups of AND gates are also appropriatelyconnected in similar fashion.

The outputs of each group of AND gates 91-100 are connected to anassociated OR gate 101-110. The outputs of each OR gate except for thefirst OR gate in sequence are connected to an associated second OR gate111, 112, A second input of each second OR gate 111, 112, is connectedto the output of the previous flip-flop in sequence, and its output isconnected to the D input of its associated flip-flop. The output of thefirst OR gate 110 is connected directly to the D input of its associatedflip-flip FF10.

The multiplexer 51 operates in response to a readout pulse from amultiplexer control 41,42, 43, or 63 to apply the ten data bits from therespective video buffer 45, 46, 47, or 61 to the D input of thecorresponding ten flip-flops FFl-FF10. The data bits are loaded into theflip-flops on the next clock pulse and on subsequent clock pulses aremoved along the sequence of flip-flops to be transferred out seriallyfrom the output of the last flip-flop in the sequence FFl to the summingnetwork 54 to become part of the video stream. The clock pulse rate isequal to the dot position scanning rate.

It can be seen that the reading out of the video buffers 45, 46, 47, and61 is independently controlled by the respective multiplexer controls41, 42, 43, and 63. Thus, the data bits from one of the buffers can beread out while those from another are in the shift register, causing thetwo characters to be superimposed on the display surface. This situationis illustrated in FIG. 7C wherein the delayed solid character issuperimposed with the fill-in half-tone character appearing in the thirdrow location and also with the solid character appearing in the fourthrow location.

Data bits for a scanline of the half-tone character are in the fill-invideo buffer 61 and data bits for the scanline of the solid characterare in the delay 1 video buffer 46. During the scanline, a fill-inreadout pulse is produced by the fill-in multiplexer control 63 applyingthe data bits for the half-tone character from the fill-in video buffer61 to the appropriate flip-flops FFl-FF10 of the shift register. Thenext clock pulse loads the data bits into the flip-flops therebyclocking the first data bit into the video stream. On the next clockpulse, the data bits each shift one flip-flop to the right and thesecond data bit for the half-tone character enters the video stream.

After six data bits or dot positions have been clocked out from theshift register a delay 1 readout pulse is produced by the delay Imultiplexer control 42 applying the data bits for the solid characterfrom the delay 1 video buffer 46 to the appropriate flip-flops FF 1-FF10of the shift register. The next clock pulse shifts the data bits for thehalf-tone character one stage to the right placing the seventh bit inthe video stream. At the same time, the data bits for the solidcharacter are loaded into the flip-flops FFl-FFIO and the first data bitfor the solid character enters the video stream.

That is, if either the data bit for the half-tone character applied to aparticular flip-flop through a previous flip-flop in the sequence or thedata bit for the solid character applied to the particular flip-flopfrom the delay 1 video buffer 46 is a 1, then the flip-flop will be setto produce an output signal. In this manner, data bits from one videobuffer are combined with or caused to overlap those from another videobuffer, and the resulting image displayed is the two characterssuperimposed as illustrated in the third row of FIG. 7C. For thisparticular example, since the solid character is all ls, it overlies andobscures the half-tone character providing the proper representation ofthe bargraph as shown in FIG. 7C.

The system also provides for handling the particular situation when thecharacter to be the fill-in character is itself being delayed and is notbeing displayed in its That location. Thiat is, a first delay code wordis in a storage position of the memory followed by an associated firstgraphic character code word in the next storage position, a second delaycode word in the next storage position, and an associated second graphiccharacter code word in the following storage position.

As illustrated in the graphic fill-in control 60 in FIG. 3, differentportions are used depending upon whether the first delay is to beprocessed by the delay arrangement 40 as a delay 1 or as a delay 2. Fora delay I, the graphic fill-in control 60 includes an AND gate 72 havingone input connected to the AND gate 71 previously described and anotherinput connected to the delay control 32. The output of AND gate 72 isconnected to the D input of a D-type flip-flop 76. The D-type flipflopis clocked at the character location scanning rate. The output of theflip-flop 76 is connected to an AND gate 79. The other input of the ANDgate 79 receives the delay 1 complete signal from the delay 1 counter34. The output of the AND gate 79 is connected to cause the D-typeflip-flop 76 to be cleared to its reset condition and also is one of theinputs to the previously mentioned OR gate 82.

A similar arrangement for the delay 2 situation includes an AND gate 73having its inputs connected to the output of AND gate 71 and to thedelay control 32. Its output is connected to the D input of a D-typeflipflop 77 which is also clocked at the character location scanningrate. The output of the D-type flip-flop 77 is connected to the input ofan AND gate 80 having its other input connected to the delay 2 counter36 to receive the delay 2 complete signal therefrom. The output of theAND gate 80 is applied to the D-type flipflop 77 to cause the flip-flopto be reset and also to one of the inputs of the OR gate 82.

The appatatus operates in the following manner assuming that the firstdelay code word and its associated graphic character code word are to beprocessed as a delay 1. The delay 1 code word and the associated graphiccharacter code word are processed in a straightforward manner withoutemploying the fill-in sections since they do not produce the combinationof the graphic and delay next signals required to activate the graphictill-in control 60. When the first character code is being applied tothe graphic generator 30, the

graphic signal from the delay, alphanumeric or graphic, and amplitudeindication register 28 occurs at the same time as the delay next signalfrom the decoder 25 for the second delay code word.

At this time, the representation of the amount of delay for the firstdelay has been placed in the delay register 31 and is holding prior tobeing transferred to the delay l counter 34. The delay control 32provides an indication that there is a delay representation in the delayregister 31 and that it will be transferred to the delay 1 counter 34.This information is applied to the AND gate 72 and is labeled as a delay1 in delay register signal. This signal passes through the OR gate 74 toinhibit the gate so that the output of the AND gate 71 does not producea signal at the D input of the D- type flip-flop 78.

Instead, the signal from the AND gate 71 passes through the AND gate 72to the D input of the D-type flip-flop 76. On the subsequent clockpulse, which occurs at the character location rate, when the first 1graphic character data is placed in the delay 1 video buffer 46 and theassociated first delay is transferred from the delay register 31 to thedelay 1 counter 34, the D-type flip-flop 76 is set to produce an outputsignal to the AND gate 79.

The D-type flip-flop 76 remains stable in this condition until such timeas the delay 1 counter 34 has counted down the amount of delay of thefirst delay and produces a delay 1 complete signal. This signal causesthe delay 1 multiplexer control 42 to read out the character data fromthe delay l video buffer 46 through the appropriate multiplexers 50 and51 or 51 to the appropriate shift registers 52 and 53 in the mannerexplained previously. This same delay 1 complete signal is applied tothe AND gate 79 in the graphic fillin control 60 causing a signal to beproduced which clears the D-type flip-flop 76 to its reset condition andpasses through the OR gate 82. The output of the OR gate 82 is a loadingsignal to the fill-in video buffer 61 causing the data being read out ofthe delay 1 video buffer 46 for display also to be loaded into thefill-in video buffer 61. The output of the OR gate 82 is also applied tothe .1 input of the J-K flip-flop causing it to be set on the next clockpulse thereto. The inhibiting connection of the OR gate 82 to the gate84 prevents the delay 1 complete signal from reaching the K input of theJ-K flip-flop 85.

The output of the J-K flip-flop 85 to the AND gate 86 permits the nextcharacter location clock pulse applied thereto to cause the fill-inmultiplexer control 63 to read out the character data in the fill-invideo buffer 61 by way of the multiplexers 50 and 51 or 51 as explainedpreviously. Also as explained previously, the fill-in video buffer 61 isrepeatedly read out by the fillin multiplexer control 63 causing theimages of the first character to be displayed in succeeding normallocations until the .l-K flip-flop 85 is reset by a delay completesignal. This resetting action occurs when the delay 2 counter 36completes the countdown for the second delay and produces a delay 2complete signal.

Thus, as shown herein, the system in accordance with the invention maybe employed to display information in the form of overlapping orcomposite bargraphs which are esthetically pleasing and exhibit a highdegree of accuracy. The capability of the system to superimposedisplayed characters permits the construction of bargraphs which mayhave their upper edges positioned accurately to within a fraction of thedimension of a character. The apparatus permits the display ofoverlapping bargraphs by providing for filling-in at certain locationsto provide continuity thus presenting readable arrangements of amultiplicity of bargraphs such as those illustrated in FIGS. 8 and 9.

While there has been shown and described what is considered a preferredembodiment of the present invention, it will be obvious to those skilledin the art that various changes and modifications may be made thereinwithout departing from the invention as defined by the appended claims.

What is claimed is:

1. A system for displaying characters on a video display means of thetype producing images on a display surface by selectively writing on thedisplay surface while repeatedly sweeping a raster scanline pattern overthe display surface, said system including in combination memory meansfor storing sata in a plurality of storage positions, each storageposition corresponding to a normal location on the display surface, saiddata being character data representing a character to be displayed orbeing delay data representing an amount of delay associated with thecharacter data stored in a particular storage position;

addressing means for reading out data from said memory means byaddressing said storage positions in a predetermined sequence; videosignal generating means coupled to said memory means and operable inresonse to character data read out of said memory means to generatevideo signal patterns for producing images related to the character dataon the display surface;

control means operable in response to character data being read out of astorage position in the memory means and in the absence of delay dataassociated therewith to cause the video signal generator to generatevideo signal patterns for producing an image of the character on thedisplay surface in its normal location corresponding to the storageposition in which the respective character data is stored;

delay means operable in response to character data being read out of astorage position in the memory means and having delay data associatedtherewith to cause the video signal generator to generate video signalpatterns for producing an image of the character on the display surfacein a location displaced from its normal location by an amount determinedby the associated delay data; and

fill-in means including first means operable to detect the reading outof delay data associated with a change in the character data being readout of the memory means, and second means coupled to the first means andto the video signal generating means and operable in response to thedetection of delay data associated with a change in the character databy the first means to cause the video signal generating means to repeatgenerating the video signal patterns for producing images related to thecharacter data.

2. A system for displaying characters in accordance with claim 1including fill-in input detection means for causing said fill-in meansto be activated in response to a predetermined input condition includingthe absence of character data in the storage position addressed next insequence after'addressing a storage position containing character data;and fill-in deactivating means for causing said fill-in means to bedeactivated in response to the subsequent reading out of character datafrom said memory means and the generating of video signal patterns inresponse thereto by the video signal generating means. 3. A system fordisplaying characters in accordance with claim 2 wherein said till-inmeans includes means for re-applying character data to said video signalgenerating means immediately subsequent to the generation of videosignal patterns for producing images related to the character data bythe video signal generating means during the tracing of a scanlinewhereby images related to the character data are repeated on the displaysurface contiguous the location of the images previously produced anddisplaced therefrom in the direction of tracing of individual scanlines.4. A system for displaying characters in accordance with claim 3 whereinsaid fill-in means includes fill-in storage means coupled to said videosignal generating means for receiving and storing character datatherefrom; fill-in storage control means for causing character data fromsaid video signal generating means to be stored in said fill-in storagemeans; and fill-in readout control means for causing character datastored in said fill-in storage means to be reapplied to said videosignal generating means whereby said video signal generating means againgenerates video signal patterns for producing images related to thecharacter data. 5. A system for displaying characters on a video displaymeans of the type producing images on a display surface by selectivelywriting on the display surface while repeatedly sweeping a rasterscanline pattern over the display surface, said system including incombination memory means for storing coded data in a plurality ofstorage positions, each storage position corresponding to a normallocation on the display surface, the storage positions being arranged inan array designating rows and columns of corresponding normal locationson the display surface, said coded data being a digital character codeword representing a character to be displayed or being a digital delaycode word representing an amount of dey; memory addressing means forreading out digital code words from the storage positions designating acolumn in sequence for each tracing of a scanline;

a digital delay code word stored in a storage position being associatedwith the digital character code word stored in the adjacent storageposition next in the sequence;

video signal generating means coupled to said memory means and operablein response to a digital character code word being read out of a storageposition in the memory means to generate video signal patterns forproducing an image of the character on the display surface;

control means operable in response to a digital character code wordbeing read out of a storage position in the memory means and in theabsence of an associated digital delay word being read out of theprevious storage position in the sequence to cause the video signalgenerating means to generate video signal patterns for producing animage of the character on the display surface in timed relationship withsignals for controlling the raster scanline pattern so that the image ofthe character is produced on the display surface in its normal locationcorresponding to the storage position in which the respective digitalcharacter code word is stored;

delay means operable in response to a digital delay code word being readout of a storage position in the memory means and an associated digitalcharacter code word being read out of the following storage position inthe sequence to cause the video signal generating means to generatevideo signal patterns for producing an image of the character on thedisplay surface in time relationship with signals for controlling theraster scanline pattern so that the image of the character is producedon the display surface in a location displaced from its normal locationin the direction of tracing of the individual scanlines by an amountdetermined by the amount of delay represented by the digital code word;and

fill-in means including first means operable to detect a digitalcharacter code word being read out of a storage position in the memorymeans and a digital delay code word being read out of the followingstorage position in the sequence, and second means coupled to the firstmeans and to the video signal generating means and operable in responseto the detection of a digital character code word being read out of astorage position and a digital delay code word being read out of thefollowing storage position to cause the video signal generating means torepeat generating the video signal patterns for producing an image ofthe character so that images of the character are repeatedly produced onthe display surface in locations between the normal location for theimage of the character and the displaced location for the image of thesubsequent character associated with the digital delay code word 6. Asystem for displaying characters in accordance with claim includingfirst character data storage means for storing data related to acharacter read out of a storage position of said memory means;

and wherein said delay means includes delay data storage means forstoring data representing an amount of delay read out of a storageposition in said memory means; delayed character data storage means forstoring data relating to the associated character read out of thefollowing storage position in sequence; said fill-in means includesfill-in character data storage means coupled to said first characterdata storage means and operable in response to a loading signal beingapplied thereto to receive and store data relating to the characterbeing read out of the first character data storage means;

said control means includes readout control means coupled to said firstcharacter data storage means and operable to read out the data relatingto the character stored in the first character data storage means and tocause the video signal generating means to generate video signalpatterns for producing an image as determined by the data relating tothe character; said delay means also includes delay readout controlmeans coupled to said delay data storage means and to said delayedcharacter data storage means and operable to read out the data relatingto the character stored in the delayed character data storage means uponcompletion of the amount of delay represented by the data stored in thedelay data storage means and cause the video signal generating means togenerate video signal patterns for producing an image as determined bythe data relating to the character; and said fill-in means also includesfill'in detection means coupled to said fill-in character data storagemeans and operable in response to a digital character code word beingread out of a storage position in the memory means and data relating tothe character being stored in the first character data storage means anda digital delay code word being read out of the following storageposition in the sequence and data representing the amount of delay beingstored in said delay data storage means to produce a loading signal whensaid readout control means reads out the data relating to the characterstored in the first character data storage means thereby storing datarelating to said character in the fill-in character data storage means;and fill-in readout control means coupled to the fill-in character datastorage means and operable to repeatedly read out the data relating tothe character stored in the fill-in character data storage means andcause the video signal generating means repeatedly to generate videosignal patterns for producing an image as determined by the datarelating to the character, the repeated reading out of data beingterminated in response to completion of the amount of delay representedby the data stored in the delay data storage means. 7. A system fordisplaying characters in accordance with claim 6 including inputdecoding means coupled to said memory means and operable to produce adelay signal in response to a digital delay code word being read out ofsaid memory means;

and wherein said delay means includes delay input control means coupledto said input decoding means and operable in response to said delaysignal to cause data representing the amount of delay to be stored insaid delay data storage means and also operable in response to saiddelay signal to cause subsequent data relating to the associatedcharacter to be stored in said delayed character data storage means; andsaid delay readout control means includes counting means coupled to saiddelay data storage means for receiving a count representative of theamount of delay stored in the delay data storage means, the countrepresenting a number of incremental divisions of the dimension of alocation on the display surface along the direction in which thescanlines are traced; said counting means being operable to receiveperiodic clock pulses and to produce an indication when the number ofclock pulses received equals the count received from said delay datastorage means; clock pulse generating means for applying periodic clockpulses to said counting means when activated, the clock pulses occurringat the rate of one clock pulse for the tracing of a scanline through oneincremental division; counting control means for applying the countrepresentative of the amount of delay stored in the delay data storagemeans to the counting means and for activating said clock pulsegenerating means when data relating to the associated character isloaded into said delayed character data storage means; and delay readoutmeans operable in response to said indication to cause the data relatingto the character stored in the delayed character data storage means tobe read out of the delayed character data storage means and the videosignal generating means to generate video signal patterns for producingan image as determined by the data relating to the character. 8. Asystem for displaying characters in accordance with claim 7 wherein saidfill-in readout control means includes means coupled to said fill-indetection means and operable in response to said loading signal to readout the data relating to the character stored in said fill-in characterdata storage means in timed relationship with the tracing of a scanlineso that the images relating to the character data are produced insuccessive normal locations along the scanline, said means being coupledto said counting means and being operable in response to an indicationtherefrom to terminate further reading out of character data from thefill-in character data storage means. 9. A system for displayingcharacters in accordance with claim 8 wherein said fill-in detectionmeans includes fill-in delay detection means coupled to said delay datastorage means and to said counting means and operable in response to afirst digital delay code word being read out of a storage position inthe memory means, an associated first digital character code word beingread out of the next storage position, a second digital delay code wordbeing read out of the next storage position, and an associated seconddigital character code word being read out of the next storage position,to produce a loading signal in response to the indication from saidcounting means when the counting means has counted the number of clockpulses equal to the count representative of the amount of delay of thefirst digital delay code word. 10. A system for displaying characters inaccordance with claim 8 wherein said video signal generating meansincludes video output means coupled to said first character data storagemeans, said delayed character data storage means, and said fill-incharacter data storage means and operable to convert character dataapplied thereto to a stream of video signals in timed relationship withthe tracing of a scanline; i said control means includes output controlmeans coupled to said video output means and operable to apply the datastored in the first character data storage means thereto in timedrelationship with the tracing of a scanline; said fill-in readoutcontrol means includes fill-in control means coupled to said videooutput means and operable to apply the data stored in the fill-incharacter data storage means thereto in timed relationship with thetracing of a scanline to cause the images to be produced in successivenormal locations on the display surface; and the delay readout means ofthe delay readout control means is coupled to said video output meansand is operable to apply the data stored in the delayed character datastorage means thereto in response to said indication from said countingmeans; whereby upon time coincidence of data being applied to the videooutput means from more than one of said data storage means, the streamof video signals generated by the video output means consists of signalsfor causing images related to the characters to be superimposed. 11. Asystem for displaying characters in accordance with claim 10 whereinsaid video output means includes a shift register having a plurality ofstages arranged in succession, the number of stages being equal to thenumber of incremental divisions of the dimension of a location on thedisplay surface along the direction in which the scanlines are traced,each stage of said shift register having an output terminal, a signalinput terminal, and a clock input terminal;

a like plurality of triads of AND gates, each triad being associatedwith a different stage of said shift register, a first input connectionof the first AND gate of each triad being connected together and coupledto said output control means of said control means, a second inputconnection of the first AND gate of each triad being coupled to thefirst character data storage means, a first input connection of thesecond AND gate of each triad being connected together and coupled tosaid fill-in control means of the till-in readout control means, asecond input connection of the second AND gate of each triad beingcoupled to the fill-in character data storage means, a first inputconnection of the third AND gate of each traid being connected togetherand coupled to said delay readout means of the delay readout controlmeans, and a second input connection of the second AND gate of eachtriad being coupled to the delayed character data storage means;

a like plurality of first OR arrangements each associated with adifferent triad of AND gates, each first OR arrangement having a firstinput connection connected to the output connection of the first ANDgate of its associated triad, a second input connection connected to theoutput connection of the second AND gate of its associated triad, and athird input connection connected to the output connection of the thirdAND gate of its associated triad;

like plurality minus one of second OR arrangements each associated witha different stage of the shift register except for the first stage inthe succession, each second OR arrangement having a first inputconnection connected to the output connection of the associated first ORarrangement, a second input connection connected to the output terminalof the previous stage in the succession, and an output connectionconnected to the signal input terminal of its associated stage, theoutput conneccharacter data storage means.

1. A system for displaying characters on a video display means of thetype producing images on a display surface by selectively writing on thedisplay surface while repeatedly sweeping a raster scanline pattern overthe display surface, said system including in combination memory meansfor storing sata in a plurality of storage positions, each storageposition corresponding to a normal location on the display surface, saiddata being character data representing a character to be displayed orbeing delay data representing an amount of delay associated with thecharacter data stored in a particular storage position; addressing meansfor reading out data from said memory means by addressing said storagepositions in a predetermined sequence; video signal generating meanscoupled to said memory means and operable in resonse to character dataread out of said memory means to generate video signal patterns forprodUcing images related to the character data on the display surface;control means operable in response to character data being read out of astorage position in the memory means and in the absence of delay dataassociated therewith to cause the video signal generator to generatevideo signal patterns for producing an image of the character on thedisplay surface in its normal location corresponding to the storageposition in which the respective character data is stored; delay meansoperable in response to character data being read out of a storageposition in the memory means and having delay data associated therewithto cause the video signal generator to generate video signal patternsfor producing an image of the character on the display surface in alocation displaced from its normal location by an amount determined bythe associated delay data; and fill-in means including first meansoperable to detect the reading out of delay data associated with achange in the character data being read out of the memory means, andsecond means coupled to the first means and to the video signalgenerating means and operable in response to the detection of delay dataassociated with a change in the character data by the first means tocause the video signal generating means to repeat generating the videosignal patterns for producing images related to the character data.
 2. Asystem for displaying characters in accordance with claim 1 includingfill-in input detection means for causing said fill-in means to beactivated in response to a predetermined input condition including theabsence of character data in the storage position addressed next insequence after addressing a storage position containing character data;and fill-in deactivating means for causing said fill-in means to bedeactivated in response to the subsequent reading out of character datafrom said memory means and the generating of video signal patterns inresponse thereto by the video signal generating means.
 3. A system fordisplaying characters in accordance with claim 2 wherein said fill-inmeans includes means for re-applying character data to said video signalgenerating means immediately subsequent to the generation of videosignal patterns for producing images related to the character data bythe video signal generating means during the tracing of a scanlinewhereby images related to the character data are repeated on the displaysurface contiguous the location of the images previously produced anddisplaced therefrom in the direction of tracing of individual scanlines.4. A system for displaying characters in accordance with claim 3 whereinsaid fill-in means includes fill-in storage means coupled to said videosignal generating means for receiving and storing character datatherefrom; fill-in storage control means for causing character data fromsaid video signal generating means to be stored in said fill-in storagemeans; and fill-in readout control means for causing character datastored in said fill-in storage means to be re-applied to said videosignal generating means whereby said video signal generating means againgenerates video signal patterns for producing images related to thecharacter data.
 5. A system for displaying characters on a video displaymeans of the type producing images on a display surface by selectivelywriting on the display surface while repeatedly sweeping a rasterscanline pattern over the display surface, said system including incombination memory means for storing coded data in a plurality ofstorage positions, each storage position corresponding to a normallocation on the display surface, the storage positions being arranged inan array designating rows and columns of corresponding normal locationson the display surface, said coded data being a digital character codeword representing a character to be displayed or being a digital delaycode word representing an amount of delay; memory adDressing means forreading out digital code words from the storage positions designating acolumn in sequence for each tracing of a scanline; a digital delay codeword stored in a storage position being associated with the digitalcharacter code word stored in the adjacent storage position next in thesequence; video signal generating means coupled to said memory means andoperable in response to a digital character code word being read out ofa storage position in the memory means to generate video signal patternsfor producing an image of the character on the display surface; controlmeans operable in response to a digital character code word being readout of a storage position in the memory means and in the absence of anassociated digital delay word being read out of the previous storageposition in the sequence to cause the video signal generating means togenerate video signal patterns for producing an image of the characteron the display surface in timed relationship with signals forcontrolling the raster scanline pattern so that the image of thecharacter is produced on the display surface in its normal locationcorresponding to the storage position in which the respective digitalcharacter code word is stored; delay means operable in response to adigital delay code word being read out of a storage position in thememory means and an associated digital character code word being readout of the following storage position in the sequence to cause the videosignal generating means to generate video signal patterns for producingan image of the character on the display surface in time relationshipwith signals for controlling the raster scanline pattern so that theimage of the character is produced on the display surface in a locationdisplaced from its normal location in the direction of tracing of theindividual scanlines by an amount determined by the amount of delayrepresented by the digital code word; and fill-in means including firstmeans operable to detect a digital character code word being read out ofa storage position in the memory means and a digital delay code wordbeing read out of the following storage position in the sequence, andsecond means coupled to the first means and to the video signalgenerating means and operable in response to the detection of a digitalcharacter code word being read out of a storage position and a digitaldelay code word being read out of the following storage position tocause the video signal generating means to repeat generating the videosignal patterns for producing an image of the character so that imagesof the character are repeatedly produced on the display surface inlocations between the normal location for the image of the character andthe displaced location for the image of the subsequent characterassociated with the digital delay code word.
 6. A system for displayingcharacters in accordance with claim 5 including first character datastorage means for storing data related to a character read out of astorage position of said memory means; and wherein said delay meansincludes delay data storage means for storing data representing anamount of delay read out of a storage position in said memory means;delayed character data storage means for storing data relating to theassociated character read out of the following storage position insequence; said fill-in means includes fill-in character data storagemeans coupled to said first character data storage means and operable inresponse to a loading signal being applied thereto to receive and storedata relating to the character being read out of the first characterdata storage means; said control means includes readout control meanscoupled to said first character data storage means and operable to readout the data relating to the character stored in the first characterdata storage means and to cause the video signal generating means togenerate video signal patterns for proDucing an image as determined bythe data relating to the character; said delay means also includes delayreadout control means coupled to said delay data storage means and tosaid delayed character data storage means and operable to read out thedata relating to the character stored in the delayed character datastorage means upon completion of the amount of delay represented by thedata stored in the delay data storage means and cause the video signalgenerating means to generate video signal patterns for producing animage as determined by the data relating to the character; and saidfill-in means also includes fill-in detection means coupled to saidfill-in character data storage means and operable in response to adigital character code word being read out of a storage position in thememory means and data relating to the character being stored in thefirst character data storage means and a digital delay code word beingread out of the following storage position in the sequence and datarepresenting the amount of delay being stored in said delay data storagemeans to produce a loading signal when said readout control means readsout the data relating to the character stored in the first characterdata storage means thereby storing data relating to said character inthe fill-in character data storage means; and fill-in readout controlmeans coupled to the fill-in character data storage means and operableto repeatedly read out the data relating to the character stored in thefill-in character data storage means and cause the video signalgenerating means repeatedly to generate video signal patterns forproducing an image as determined by the data relating to the character,the repeated reading out of data being terminated in response tocompletion of the amount of delay represented by the data stored in thedelay data storage means.
 7. A system for displaying characters inaccordance with claim 6 including input decoding means coupled to saidmemory means and operable to produce a delay signal in response to adigital delay code word being read out of said memory means; and whereinsaid delay means includes delay input control means coupled to saidinput decoding means and operable in response to said delay signal tocause data representing the amount of delay to be stored in said delaydata storage means and also operable in response to said delay signal tocause subsequent data relating to the associated character to be storedin said delayed character data storage means; and said delay readoutcontrol means includes counting means coupled to said delay data storagemeans for receiving a count representative of the amount of delay storedin the delay data storage means, the count representing a number ofincremental divisions of the dimension of a location on the displaysurface along the direction in which the scanlines are traced; saidcounting means being operable to receive periodic clock pulses and toproduce an indication when the number of clock pulses received equalsthe count received from said delay data storage means; clock pulsegenerating means for applying periodic clock pulses to said countingmeans when activated, the clock pulses occurring at the rate of oneclock pulse for the tracing of a scanline through one incrementaldivision; counting control means for applying the count representativeof the amount of delay stored in the delay data storage means to thecounting means and for activating said clock pulse generating means whendata relating to the associated character is loaded into said delayedcharacter data storage means; and delay readout means operable inresponse to said indication to cause the data relating to the characterstored in the delayed character data storage means to be read out of thedelayed character data storage means and the video signal generatingmeans to generate video signal patterns for producing an image asdetermined by the datA relating to the character.
 8. A system fordisplaying characters in accordance with claim 7 wherein said fill-inreadout control means includes means coupled to said fill-in detectionmeans and operable in response to said loading signal to read out thedata relating to the character stored in said fill-in character datastorage means in timed relationship with the tracing of a scanline sothat the images relating to the character data are produced insuccessive normal locations along the scanline, said means being coupledto said counting means and being operable in response to an indicationtherefrom to terminate further reading out of character data from thefill-in character data storage means.
 9. A system for displayingcharacters in accordance with claim 8 wherein said fill-in detectionmeans includes fill-in delay detection means coupled to said delay datastorage means and to said counting means and operable in response to afirst digital delay code word being read out of a storage position inthe memory means, an associated first digital character code word beingread out of the next storage position, a second digital delay code wordbeing read out of the next storage position, and an associated seconddigital character code word being read out of the next storage position,to produce a loading signal in response to the indication from saidcounting means when the counting means has counted the number of clockpulses equal to the count representative of the amount of delay of thefirst digital delay code word.
 10. A system for displaying characters inaccordance with claim 8 wherein said video signal generating meansincludes video output means coupled to said first character data storagemeans, said delayed character data storage means, and said fill-incharacter data storage means and operable to convert character dataapplied thereto to a stream of video signals in timed relationship withthe tracing of a scanline; said control means includes output controlmeans coupled to said video output means and operable to apply the datastored in the first character data storage means thereto in timedrelationship with the tracing of a scanline; said fill-in readoutcontrol means includes fill-in control means coupled to said videooutput means and operable to apply the data stored in the fill-incharacter data storage means thereto in timed relationship with thetracing of a scanline to cause the images to be produced in successivenormal locations on the display surface; and the delay readout means ofthe delay readout control means is coupled to said video output meansand is operable to apply the data stored in the delayed character datastorage means thereto in response to said indication from said countingmeans; whereby upon time coincidence of data being applied to the videooutput means from more than one of said data storage means, the streamof video signals generated by the video output means consists of signalsfor causing images related to the characters to be superimposed.
 11. Asystem for displaying characters in accordance with claim 10 whereinsaid video output means includes a shift register having a plurality ofstages arranged in succession, the number of stages being equal to thenumber of incremental divisions of the dimension of a location on thedisplay surface along the direction in which the scanlines are traced,each stage of said shift register having an output terminal, a signalinput terminal, and a clock input terminal; a like plurality of triadsof AND gates, each triad being associated with a different stage of saidshift register, a first input connection of the first AND gate of eachtriad being connected together and coupled to said output control meansof said control means, a second input connection of the first AND gateof each triad being coupled to the first character data storage means, afirst input connection of the second AND gAte of each triad beingconnected together and coupled to said fill-in control means of thefill-in readout control means, a second input connection of the secondAND gate of each triad being coupled to the fill-in character datastorage means, a first input connection of the third AND gate of eachtraid being connected together and coupled to said delay readout meansof the delay readout control means, and a second input connection of thesecond AND gate of each triad being coupled to the delayed characterdata storage means; a like plurality of first OR arrangements eachassociated with a different triad of AND gates, each first ORarrangement having a first input connection connected to the outputconnection of the first AND gate of its associated triad, a second inputconnection connected to the output connection of the second AND gate ofits associated triad, and a third input connection connected to theoutput connection of the third AND gate of its associated triad; a likeplurality minus one of second OR arrangements each associated with adifferent stage of the shift register except for the first stage in thesuccession, each second OR arrangement having a first input connectionconnected to the output connection of the associated first ORarrangement, a second input connection connected to the output terminalof the previous stage in the succession, and an output connectionconnected to the signal input terminal of its associated stage, theoutput connection of the first OR arrangement associated with the firststage in the succession being connected to the signal input terminal ofits associated stage; means connected to the clock input terminals forapplying clock pulses thereto, the clock pulses occurring at the rate ofone clock pulse for the tracing of a scanline through one incrementaldivision; a video signal output terminal connected to the outputterminal of the final stage of the succession; and fill-in connectionmeans for coupling the output connection of each first OR arrangement tosaid fill-in character data storage means.